Although the characteristics of the circuit have been decided and at least partly also developed in Europe, the design of the actual physical implementation is handled by the Indian Open-Silicon Research.
Europe is slowly beginning to wake up to the reality that high-performance HPC (High Performance Computing) processors, accelerators, and computing circuits are being developed in North America and Asia. As a result, the European Processor Initiative, or EPI, was established, the first step of which is the system circuits of the Rhea family.
Rhea system circuits will be based on both ARM and RISC-V architectures and its development will be led by SiPearl. The company has now announced, together with Open-Silicon Research, OpenFive’s Indian wing, a collaboration agreement that OSR will be responsible for the physical implementation of the system circuit. The system circuit will also utilize OSR’s expertise in 2.5D packaging, as well as the inter-circuit gateways and HBM2E controllers developed by the company.
The exact technical details of Europe’s first HPC system circuit are still partly unclear, but according to a roadmap published by EPI, it will utilize Arm’s Zeus server kernels, which will have as many as 72 in total, as well as a number of different accelerators. At this stage, the circuit is known to include an EPAC-christened accelerator based on the RISC-V architecture, a Multi-Purpose Processor Array (MPPA) accelerator based on a large number of small cores, a programmable embedded FPGA (eFPGA, Embedded Field-Programmable Gate Array) and separate cryptographs. The memory needs of the system circuit are met by four HBM2E memory controllers and 4-6 DDR5 memory controllers.
Rhea system circuits will be fabricated using TSMC’s 6-nanometer N6 fabrication process. The system circuit is expected to be completed later this year.
Source: SiPearl (PDF),
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